Complementary Field Effect Transistor (FET) logic circuits, and in particular Complementary Metal Oxide Semiconductor (CMOS) logic circuits have become increasingly popular for integrated circuit logic, among other reasons because of their high circuit density and low power dissipation. A typical CMOS logic gate is illustrated in FIG. 1 of U.S. Pat. No. 3,911,289 to Takemoto entitled MOS Type Semiconductor IC Device. A CMOS logic gate typically includes a driving stage having a plurality of FETs of a first conductivity type connected in parallel and a load stage comprising a like plurality of serially connected FETs of opposite conductivity type. Each logic signal input is applied simultaneously to a pair of transistors, one driver and one load.
Unfortunately, the serial connection of the load transistors in conventional CMOS logic gates reduces the toggle rate or switching speed of the gate and also reduces the number of inputs which may be applied to the gate (referred to as "fan-in"). To overcome these problems an "all parallel" CMOS gate design has heretofore been proposed. One all parallel CMOS logic gate is described in FIG. 3A of the aforementioned U.S. Pat. No. 3,911,289, in which the serial load transistors are replaced by a first load which may be an MOS transistor or a resistor, and a second load comprising an MOS transistor having opposite conductivity type from the driver stage transistors.
A particularly high performance all-parallel logic family is described in application Ser. No. 7/338,280 filed on Apr. 14, 1989 to the present inventor Albert W. Vinal and entitled High Speed Complementary Field Effect Transistor Logic Circuits, now U.S. Pat. No. 5,001,367, which is assigned to the assignee of the present invention, the disclosure of which is hereby incorporated herein by reference. A high speed, high density low power dissipation complementary FET logic circuit is disclosed, in which the voltage transfer function of the logic gate's complementary FET inverter output stage is deliberately skewed to dramatically decrease the lift-off interval for the logic gate and thereby dramatically increase the speed of the gate. A switching speed of 500 megahertz or greater may be obtained, which is a factor of five or more greater than prior art all-parallel logic designs, for example the design disclosed in the aforementioned U.S. Pat. 3,911,289.
Notwithstanding the above described improvement, there is a continued need for higher performance all-parallel logic designs. In particular, there is a continued need for a high speed logic circuit family in which the rise and delay times of the gate are minimized. In other words, the internal delay of the gate in providing a logic output signal which accurately reflects the state of the logic input signals must be minimized.
Another major limitation on the speed of complementary FET logic inputs is the inherent difference between the saturation current of P-channel devices compared to those of N-channel devices. In particular, silicon P-channel FET devices deliver about half the saturation current as comparable N-channel FET devices. The lower saturation current and corresponding lower carrier mobility of P-channel device limits the overall speed of the logic gate.
Finally, the internal capacitance of the logic gate also is a major roadblock in increasing its speed. The internal capacitance of the gate also typically limits the number of logic inputs which can be handled by a single gate (fan-in). Applications that require large numbers of logical inputs, such as decoding operations, therefore typically require "trees" of cascaded logic gates, which dramatically increase the overall delay time.